6.10 System Interface Buffers

Cached Request Buffer


The System interface contains a four-entry cached request buffer. This buffer holds the status of the four possible outstanding processor cached requests, including processor block read and upgrade requests. The relative order of the requests is maintained in the cached request buffer.

External coherency requests probe the cached request buffer to detect conflict conditions.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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